? semiconductor components industries, llc, 2015 july, 2015 ? rev. 0 1 publication order number: niv1161/d niv1161, nis1161 esd protection with automotive short-to- battery blocking low capacitance esd protection with short?to?battery blocking for automotive high speed data lines the nis/niv1161 is designed to protect high speed data lines from esd as well as short to vehicle battery situations. the ultra?low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines while the low r ds(on) fet limits distortion on the signal lines. the flow?through style package allows for easy pcb layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as usb and lvds protocols. features ? low capacitance (0.65 pf typical, i/o to gnd) ? diode capacitance matching between i/o?s: 1% typical ? optimized layout for excellent high speed signal integrity ? protection for the following iec standards: iec 61000?4?2 (level 4) ? low esd clamping voltage ? niv prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? this is a pb?free device typical applications ? automotive high speed signal pairs ? usb2.0/3.0 ? lvds ? hdmi ? apix2 absolute maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j(max) ?55 to +150 c storage temperature range tstg ?55 to +150 c drain?to?source v oltage v dss 30 v gate?to?source v oltage v gs 10 v lead temperature soldering t sld 260 c iec 61000?4?2 contact (esd) iec 61000?4?2 air (esd) esd esd 8 15 kv kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. wdfn6 case 511cb marking diagram www. onsemi.com v6 = specific device code m = date code v6 m 1 device package shipping ? ordering information niv1161mttag wdfn?6 (pb?free) 3000 / tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. pin 2 ? 5 v pin 2 ? 5 v pin 5 ? gnd pin 6 pin 4 d+ d? pin 3 d? host pin 1 d+ host pin configuration and schematics 1 2 3 6 5 4 6 4 (top view) NIS1161MTTAG wdfn?6 (pb?free) 3000 / tape & ree l
niv1161, nis1161 www. onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 5 16 v breakdown v oltage v br i t = 1 ma, i/o pin to gnd 16.5 v reverse leakage current i r v rwm = 5 v, i/o pin to gnd 1.0 a clamping v oltage v c i pp = 1 a, i/o pin to gnd (8 x 20 s pulse) 26 v clamping voltage (note 1) v c iec61000?4?2, 8 kv contact see figures 1 & 2 clamping voltage tlp (note 2) v c i pp = 8 a i pp = 16 a i pp = ?8 a i pp = ?16 a 34 55 ?5.2 ?10 v v v v junction capacitance match c j v r = 0 v, f = 1 mhz between i/o1 to gnd and i/o2 to gnd 1.0 % junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd (pin 7 to gnd, pin 9 to gnd) 0.65 pf drain?to?source breakdown v oltage v br(dss) v gs = 0 v, i d = 100 a 30 v drain?to?source breakdown v oltage temperature coef ficient v br(dss) / t j reference to 25 c, i d = 100 a 27 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 30 v 1.0 a gate?to?source leakage current i gss v ds = 0 v, v gs = 5 v 1.0 a gate threshold voltage (note 3) v gs(th) v ds = v gs , i d = 100 a 0.1 1.0 1.5 v gate threshold voltage t emperature coefficient v gs(th) / t j reference to 25 c, i d = 100 a ?2.5 mv/ c drain?to?source on resistance r ds(on) v gs = 4.5 v, i d = 125 ma 1.4 7.0 v gs = 2.5 v, i d = 125 ma 2.3 7.5 forward t ransconductance g fs v ds = 3.0 v, i d = 125 ma 80 ms switching turn?on delay time (note 4) t d(on) v gs = 4.5 v, v ds = 24 v i d = 125 ma, r g = 10 v 9 ns switching turn?on rise time (note 4) t r 41 ns switching turn?of f delay time (note 4) t d(off) 96 ns switching turn?of f fall time (note 4) t f 72 ns drain?to?source forward diode v oltage v sd v gs = 0 v, i s = 125 ma 0.79 0.9 v 3 db bandwidth f bw r l = 50 5 ghz product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. for test procedure see figures 3 and 4 and application note and8307/d. 2. ansi/esd stm5.5.1 electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. 3. pulse test: pulse width 300 s, duty cycle 2% 4. switching characteristics are independent of operating junction temperatures.
niv1161, nis1161 www. onsemi.com 3 figure 1. iec61000?4?2 +8kv contact esd clamping voltage figure 2. iec61000?4?2 ?8kv contact esd clamping voltage application today?s connected cars are using multiple high speed signal pair interfaces for various applications such as infotainment, connectivity and adas. the electrical hazards likely to be encountered in these automotive high speed signal interfaces include damaging esd and transient events which occur during manufacturing and assembly, by vehicle occupants or other electrical circuits in the vehicle. the major documents discussing esd and transient events as far as road vehicles are concerned are iso 10605 (road vehicles ? test methods for electrical disturbances from electrostatic discharge) which describes esd test methods and iso 7637 (road vehicles ? electrical disturbances from conduction and coupling) for effects caused by other electronics in the vehicle. is0 10605 is based on iec 61000?4?2 industry standard, which specifies the various levels of esd signal characteristics, but also includes additional vehicle?specific requirements. further, oem specific test requirements are usually also imposed. in addition, these high speed signal pairs require protection from short?to?battery (which goes up to 16 vdc) and short?to?ground faults. a suitable protection solution must satisfy well known constraints, such as low capacitive loading of the signal lines to minimize signal attenuation, and also respond quickly to sur ges and transients with low clamping voltage. in addition, small package sizes help to minimize demand for board?space while providing the ability to route the trace signals with minimal bending to maintain signal integrity. the niv1161 provides a solution to these high speed signal interface protections from esd as well as short?to? battery situations. the esd?protection is designed to meet the iec61000?4?2 level 4 with a low i/o?to?ground capacitance of 0.65 pf typical. capacitances are closely matched to preserve signal integrity. low dynamic resistance allows very low clamping voltages, and the breakdown voltage of 16.5 v allows the device to survive a short?to?battery condition, which ranges from 9 v to 16 v. the series fets are designed with very low on?state resistance (r ds(on) ), and feature an internal layout that allows flow?through design to maintain high?speed signal integrity. the threshold voltage of 1.0 v allows operation at low gate?drive voltages consistent with usb, lvds and other low level signals.
niv1161, nis1161 www. onsemi.com 4 typical mosfet performance curves t j = 150 c 0 0.9 4.0 0.5 v ds , drain?to?source voltage (v) i d, drain current (a) 0.7 0.2 0 figure 1. on?region characteristics 0 2.0 4.0 figure 2. transfer characteristics v gs , gate?t o?source voltage (v) 1.0 8.0 figure 3. on?resistance vs. gate?to?source voltage v gs, gate voltage (v) r ds(on), drain?to?source resist ance ( ) i d, drain current (a) figure 4. on?resistance vs. drain current and gate voltage ?50 0 ?25 25 1.2 0.7 0.6 50 150 figure 5. on?resistance variation with temperature t j , junction temperature ( c) 2.0 t j = ?55 c 75 i d = 125 ma v gs = 4.5 v r ds(on), drain?to?source resistance (normalized) t j = 25 c r ds(on), drain?to?source resist ance ( ) 1.3 v gs = 2.5 v v gs = 4.5 v 1.5 3.5 0.1 25 figure 6. drain?to?source leakage current vs . voltage v ds , drain?to?source vol tage (v) 15 i dss , leakage (na) t j = 150 c t j = 125 c 10 100 v ds = 5 v 20 2.0 v 0.5 1.8 v 3.0 3 0 1.2 1.0 v gs = 10 v 10 125 100 0 5.0 10 5 3.0 1.5 1.5 5.0 4.5 t j = 25 c i d = 125 ma i d, drain current (a) 1.9 1000 2.4 v 3.5 1.0 1.0 8.0 0.1 0 0.7 0.5 10 4.0 1. 2 0.8 1.4 0.9 1.6 1.1 1.8 0.8 0.6 0.1 0.3 0.9 0.6 0.1 0 0.4 1.2 0.5 3.0 0.4 1.1 1.0 2.0 2.5 3.5 4.5 2.2 v 2.8 v 2.6 v 3.0 v 3.5 v 4.0 v 5.0 v 4.5 v 2.5 4. 5 0.2 0.3 0.5 0.7 0.8 1.0 1.1 2.5 4.0 2.0 3.0 4.0 6.0 7.0 9.0 0.2 0.3 0.4 0.6 0.8 0.9 1.0 1.1 2.0 3.0 5.0 6.0 7.0 9.0 t j = 125 c t j = ?55 c t j = 25 c t j = 125 c t j = 25 c t j = ?55 c 1.0 1.5 1.7 t j = 85 c 1
niv1161, nis1161 www. onsemi.com 5 package dimensions notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.25 mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. seating plane d e 0.10 c a3 a a1 0.10 c wdfn6 2x2, 0.65p case 511cb issue o dim a min max millimeters 0.70 0.80 a1 0.00 0.05 a3 0.20 ref b 0.25 0.35 d 2.00 bsc d2 0.55 0.65 0.55 0.65 e 2.00 bsc e2 e 0.65 bsc 0.20 0.30 l pin one reference 0.08 c 0.10 c note 4 a 0.10 c l e d2 e2 b b 3 6 5x 1 4 0.05 c mounting footprint bottom view recommended dimensions: millimeters l1 detail a l alternate constructions l detail a detail b a b top view c side view --- 0.15 l1 5x 0.44 2.30 0.80 1.72 0.65 pitch 5x 0.35 1 package outline 6x m m ??? detail b mold cmpd exposed cu alternate terminal constructions ?? a 0.10 cb 2x 2x b2 a 0.10 cb f l2 g 2x ??? ??? b2 0.35 0.45 0.55 0.65 l2 f 0.52 bsc g 0.20 bsc 2x 0.67 0.48 2x 0.67 0.54 on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or othe r applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death ma y occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidi aries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of per sonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. sci llc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 niv1161/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative
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